The invention relates to a raster scan, computer controlled video display system for presenting an image to an observer on a video display apparatus, which system includes a Z-buffer for storing Z values to enable the computer controlled video display system to present a 3-dimensional representation of an image to the observer. More specifically, the invention relates to a method for updating the Z-buffer with new Z values to replace old Z values.
Computer controlled video display systems which utilize the conventional raster scan technique in their operation, present a 3-dimensional representation of an image to an observer by, among other things, utilizing a Z-buffer which contains the information that indicates whether one object on the screen is in front of or behind another object. That is, the Z-buffer contains information for each pixel on the screen to indicate whether the object will be hidden (e.g. when behind another object or surface) or can be seen. FIG. 5 shows a screen 200 of a video display apparatus, such as a conventional RGB video monitor or a liquid crystal display device. An orthogonal coordinate system having X, Y and Z axes is shown overlaid onto the video screen 200. It will be appreciated that such axis (i.e. X axis 201, Y axis 202 and Z axis 203) will not normally appear on the screen 200 during normal operation of the computer controlled video display system. The origin 204 of the axis is shown in the upper left corner of the display area and has been assigned the coordinate (0, 0, 0). It will be understood that the screen 200 of the video display apparatus is coupled in the conventional manner to a computer controlled display system to receive the pixel values (after digital to analog conversion) from the frame buffer, which pixel values represent the color and intensity for each pixel in the image.
In the conventional raster scan technique ("rasterization"), each row of pixels, such as row 205 is drawn as the electron beam of the video display apparatus is scanned from the far left edge of the row to the far right edge of the row. Thus, for example row Yo, shown as row 205, will be scanned from X=0 to the maximum value of X (X.sub.max).
These conventional computer controlled video display systems typically have a frame buffer and a Z-buffer. The frame buffer is a memory (e.g. DRAM or SRAM) which holds the digital representation of the color and intensity for each pixel in the image. The frame buffer is also referred to as a video bitmap. The Z-buffer is a memory that holds one number for each pixel in the frame buffer. The value of this number indicates the distance between the observer and the object being displayed at the pixel. As shown in FIG. 5, a small Z value indicates that the object is closer to the observer. Conversely, it is possible to have a system where a large Z value indicates that the object is closer to the observer.
The conventional process of updating a Z-buffer according to the prior art will now be described with reference to FIG. 1. FIG. 1 shows in block diagram form a high performance graphics system which is part of a computer system. The graphics subsystem includes a graphics update controller 1 and a frame buffer 10 and a Z-buffer 11. The graphics update controller 1 of FIG. 1 controls the updating of the frame buffer 10 and the updating of the Z-buffer 11; the graphics subsystem shown in FIG. 1 is a conventional system found on high performance workstations such as the IRIS 4D/60 workstation marketed by the Assignee of the present invention. Other well known graphics subsystems utilizing a Z-buffer along with a frame buffer are well known and operate in a similar manner as the graphics subsystem shown in FIG. 1.
For a group of pixels in a scan line ("row"), the graphics update controller 1 calculates new pixel values and new Z values for each pixel location across the group of pixels in the scan line, which typically includes a plurality of pixel locations. The graphics update controller 1 will typically calculate new pixel and Z values for an entire scan line. For example, if each scan line includes 512 pixel locations (i.e. X may have a value equal to any integer between and including 1 to 512) then the graphics update controller 1 calculates in the conventional manner a new pixel value and a new Z value for each pixel location. Each pixel location already displayed on the display apparatus will have an old Z value and an old pixel value which are stored respectively in the Z-buffer and the frame buffer. For each pixel location the graphics update controller 1 performs the following four steps. Firstly, the graphics update controller 1 reads the old Z value in the Z-buffer 11 which corresponds to the current pixel which is being or has been computed. Secondly, the graphics update controller 1 compares the old Z value read from the Z-buffer 11 to the new Z value being calculated for the current pixel location to determine if the current pixel being calculated is closer to the observer than the pixel already stored in the frame buffer 10. Thirdly, the new pixel value is written into the frame buffer for the current pixel location if the new pixel for that pixel location is closer to the observer than the pixel already stored in the frame buffer 10. That is, in a typical implementation, the graphics update controller 1 determines whether the new Z value for the current pixel location is less than the old Z value for that pixel location; if it is less than, then the graphics update controller 1 addresses the appropriate pixel location for the current pixel via address and control bus 12 while supplying the new pixel value over the data buses 14 and 18. In the fourth step, the graphics update controller 1 writes the new Z value for the current pixel location into the Z-buffer 11 when the new pixel at that location is closer to the observer than the old pixel which was stored in the frame buffer 10. If the new Z value is not less than the old Z value, then no changes are made to the old pixel value and old Z value in the buffers (because the old pixel is in front of the new pixel) and the graphics update controller moves to the next pixel location.
This four step process is then repeated for the next pixel. Thus, for the next pixel location, the new pixel value is computed along with the new Z value for that pixel. Then, the old Z value is read from the Z-buffer 10 and compared to the new Z value to determine whether, for that pixel location, the new pixel is closer to the observer than the old pixel. If the new pixel is closer than the old pixel, then the frame buffer is updated with the new pixel value and the Z-buffer is updated with the new Z value. It will be appreciated from the graphics subsystem shown in FIG. 1, that since the frame buffer 10 and the Z-buffer 11 share a data bus 14 and an address and control bus 12, that only one buffer can be read from or written to at one point in time. In this invention, a graphics subsystem architecture is disclosed that allows the first three steps to be pipelined so that all three may occur simultaneously or substantially simultaneously for different pixels. Moreover, according to the method of the present invention, the Z-buffer is updated only after determining the existence of a contiguous group of pixel locations requiring updating of the Z-buffer. This method reduces the amount of additional time required to update the Z-buffer and hence improves the speed with which images may be manipulated and viewed on the video display system. Before discussing the detailed architecture and method of the present invention, it will be instructive to describe the architecture of the prior art graphics subsystem shown in FIG. 1.
Prior art graphic subsystems that use a Z-buffer typically have an architecture such as that shown in FIG. 1. One distinguishing feature of this prior art architecture is that the Z-buffer and frame buffer share a common data bus and also share a common address and control bus. Thus, frame buffer 10 and Z-buffer 11 share the common data bus 14 and also share the common address and control bus 12. In this prior art system, the graphics update controller performs all four of the steps described above for one pixel before moving on to the next pixel. The frame buffer 10 and Z-buffer 11 are refreshed if they are dynamic RAM (DRAM) using conventional, well known memory refresh techniques which are performed by the graphics update controller 1. The video display apparatus is also refreshed by conventional, well known video refresh techniques that are performed by the graphics update controller 1 which accesses pixels from the frame buffer and outputs them through bus 17 to conventional video display circuitry (e.g. digital to analog converters) and the video display apparatus such as a computer monitor. In order not to unnecessarily obscure the details of the present invention, such conventional, well known circuitry will not be described herein.
The graphics update controller 1 may be a general purpose microprocessor or a more specifically designed graphics controller chip which receives commands and graphics data from the main CPU of the computer through bus 6. The main CPU will typically provide a command such as drawing a line along a scan line from a starting X location to an ending X location along that scan line, which command will be recognized by the graphics update controller 1. In addition, the main CPU will provide certain graphics data which is stored in the register 2, which data typically includes the original pixel value (pixel.sub.s) for the first pixel to be drawn (which pixel value represents digitally the color and intensity of the first pixel), and the starting X, Y, and Z locations of the original pixel (X.sub.s, Y.sub.s and Z.sub.s), and the ending X location and the change in Z (delta Z) and the change in the pixel value (delta pixel) over the length of the line being drawn by the graphics update controller 1. The command being stored in register 2 may be subroutine entry values in the program storage 5 which values the ALU and control unit 3 retrieves from register 2 and uses to enter the appropriate subroutine in the program storage 5. The memory 4 in graphics update controller 1 is utilized as a scratch pad memory and to receive the new computed values for the new pixel and the new Z value for each pixel location. The bus 6 typically includes a conductor means which indicates to the main CPU a wait state while the graphics update controller 1 processes the previous command from the beginning X value to the ending X value. While the wait state is active, the main CPU refrains from supplying further commands and graphics data to the graphics update controller 1.
The graphics update controller 1 in a typical prior art implementation will calculate, for each pixel location after the first pixel location X.sub.s, a new pixel value by adding for each pixel location the delta pixel value to the pixel value in the prior pixel location. Thus, for example, for the pixel location X.sub.s +1 the pixel value will be pixel.sub.s +delta pixel; for the second pixel location at pixel location X.sub.s +2, the pixel value will be pixel.sub.s +2 (delta pixel). This incremental addition of delta pixel to each proceeding pixel value will continue through the whole range of X's which the main CPU has specified will be drawn for a particular row or portion of a row of pixels. The new Z-buffer values are calculated by adding delta Z to each preceding Z value, where the starting Z value is Z.sub.s. After calculating the new Z value for a particular pixel location, the old Z value is read from the Z-buffer 11 by presenting the address for that Z value on the address and control bus 12, thereby causing the output of the old Z value for that pixel location through data bus 14 and bus 18 into the graphics update controller 1. The old Z value for the particular pixel location is then compared to the new Z value for that particular pixel location. If the pixel just calculated (with its corresponding new pixel value) is closer to the observer than the pixel already in the frame buffer, then the frame buffer 10 is updated with the new pixel value and the Z-buffer 11 is updated with the new Z value. Thus, in a typical implementation, the ALU and control unit 3 reads the old Z value and compares the new and old Z values to determine whether the new Z value is less than the old Z value for the particular pixel location being updated. If the new Z value is not less than the old Z value then the pixel value in frame buffer 10 is not updated and similarly the old Z value in Z-buffer 11 for that pixel location is not updated. However, if the new Z-buffer value for the current pixel location is less than the old Z value for that pixel location then the ALU and control unit 3 causes the address corresponding to that pixel location to be applied through address and control bus 12 to the frame buffer 10 while the pixel value is applied to data bus 14 through bus 18 to thereby write the new pixel value into the frame buffer 10 at the appropriate location. Then, the Z-buffer is updated by the graphics update controller 1 when the ALU and control unit 3 causes the appropriate address of the Z value for that pixel location to appear on the address and control bus 12 while the new Z data is presented over buses 18 and then the data bus 14, thereby writing the new Z value into the Z-buffer 11. After updating the frame buffer 10 and the Z-buffer 11, the graphics update controller 1 moves to the next pixel location for the same four steps described above, unless the graphics update controller 1 has finished executing the last command, in which case it deactivates the wait state signal to the main CPU and looks for the next command and graphics data from the main CPU.
The prior art graphics system shown in FIG. 1 is typically found on high performance graphics workstations, such as the IRIS 4D/60. These graphics systems while providing high performance, suffer from the fact that only one buffer (either the frame buffer or the Z-buffer) can be addressed and only one buffer can output data or receive data at the same time. Moreover, the operations of the four steps described above are performed sequentially for each pixel location and then performed again for each subsequent pixel location with no overlapping or interleaving of operations to provide for parallel processing. Graphics architectures have been described which solve these problems by utilizing a separate address and control line for the frame buffer which is distinct from the address and control line for the Z buffer while also utilizing a dual port Z-buffer having a port for Z data in and a port for Z data out (see, for example, the article entitled "A 32b 3-D Graphic Processor Chip with 10M Pixels/S Guaraud Shading", 1988 IEEE International Solid-State Circuits Conference, pp. 168-169, 132). However, these graphics processing chips fail to efficiently overlap operations and are also more costly than a single ported Z-buffer because fewer buses are required and typically cheaper memory chips are available for single ported memory applications.
Accordingly, it is an object of the present invention to provide an efficient graphics architecture that utilizes parallel operations which are overlapped (interleaved) to increase the speed of the unit while at the same time providing a cost efficient architecture and method for updating a single ported Z-buffer memory.